IBM and Samsung have teamed up to develop a new vertical transistor architecture that could help overcome certain limitations with the current standards and pave the way for future chip design.
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With the Vertical Transport Field Effect Transistors (VTFET) approach, transistors are built perpendicular to the surface of the chip, unlike traditional approaches, such as fin field effect transistors (FinFET), where they are layered along a chip’s surface, taking up more space.
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The new architecture could address scaling barriers as chip designers attempt to pack more transistors into a finite area. Moreover, it could facilitate greater current flow with less wasted energy, with the electric current flowing up-and-down instead of side-to-side, according to the chip makers.
The companies claim the VTFET design may be able to deliver a two times improvement in performance or an 85% reduction in energy use as compared to scaled FinFET alternatives.
Besides, the new approach offers a pathway to the continuation of Moore’s Law, the principle that the number of transistors incorporated in a densely populated integrated circuit chip will approximately double every two years.
Earlier this year, IBM had announced 2nm chip technology , which according to the company, will allow a chip to fit up to 50 billion transistors in a space the size of a fingernail.
“We believe that the VTFET design represents a huge leap forward toward building next-generation transistors that will enable a trend of smaller, more powerful and energy-efficient devices in the years to come,” the tech giant said in a blog post.
Last week, Intel unveiled its work in essential scaling technologies for delivering more transistors in future product offerings.
