Two electronic chip manufacturing units, which entail a combined investment of Rs.51,550 crore, and would enjoy government subsidy, are likely to be operational in the next two years.
Two consortia — one led by Jaiprakash Associates in association with IBM, and the other led by Hindustan Semiconductor — have proposed setting up these plants.
Communications and IT Minister Kapil Sibal said the setting up of electronic chip facilities would also be of the nation’s strategic purpose as chips had security implications.
“There are strategic sectors like atomic energy sector, space, defence and power. In all of these you need chips. There are security considerations. It will serve our strategic purpose. There are security considerations. The fabs should be operational in about two years from now,” Mr. Sibal said here. At present, there is no electronic chip manufacturing or semiconductor wafer fabrication plant in India. Over 90 per cent of the domestic electronic requirement is met through imports.
The government will also hold 11 per cent stake in each project, while technology providers are required to hold 10 per cent stake.
Department of Electronics and Information Technology Secretary J Satyanarayana said: “One plant is proposed by a consortium led by Jaiprakash Associates, along with IBM Microelectronics and the system integrator is Tower Jazz. The outlay of the proposed fab is about Rs.26,300 crore.” This unit is likely to come up in Greater Noida in Uttar Pradesh.
“The other plant is from Hindustan Semiconductor Manufacturing Corporation (HSMC) along with France-based ST Microelectronics and Silterra (Malaysia). The outlay of this proposed fab is about Rs.25,250 crore,” Mr. Satyanarayana said. The proposed location of this plant is in Gujarat.
The government is yet to work out the details of subsidy the proposed projects will enjoy. Subsidy will depend on detailed project report to be submitted by the two consortia.
Mr. Sibal said that the about 60 per cent of incentives approved by Cabinet were already covered under existing policies. In addition to this, the Finance Ministry had agreed to give them status under Section 35 AD of I-T Act which meant capital investment amount would be set off against profit.
“They will be given interest-free loan. This along with recognition under Sec. 35 AD will constitute balance 40 per cent of incentives to be provided to them,” Mr. Sibal said.
Also, the loan amount given to the companies would be converted into 11 per cent equity in these projects, Mr. Satyanarayana said.
Mr. Sibal said that electronic chip manufacturing was highly capital-intensive business and had long gestation period.
“No body was interested in setting up wafer fab here unless you give them large concessions. It is zero duty in any country. We had to attract investors,” he said.
Joint Secretary in the Department of Electronics and Information Technology Ajay Kumar said that the plants would start making chip size of 90, 65 and 45 nanometers (NM) in the first phase, phase 2 will see 28 NM and it would go down to 22 NM in phase 3.
