Karnataka

IISc researchers develop design framework for next generation analog chipsets  

The researchers said that in applications that don’t require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.

The researchers said that in applications that don’t require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.

Researchers at the Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computing chipsets that could be faster and require less power than the digital chips found in most electronic devices.   

Using a novel design framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). This type of chipset can be especially helpful for Artificial Intelligence (AI)-based applications like object or speech recognition – like Alexa or  Siri – or those that require massive parallel computing operations at high speeds, an IISc release said.

Most electronic devices use digital chips because the design process is simple and scalable. “But the advantage of analog is huge. You will get orders of magnitude improvement in power and size,” explained Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the efforts to develop the analog chipset. In applications that don’t require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.  

But there are technology hurdles; unlike digital chips, testing and co-design of analog processors is difficult. As analog chips don’t scale easily, they need to be individually customised when transitioning to the next generation technology or to a new application, and their design is expensive. Another challenge is that trading off precision and speed with power and area is not easy when it comes to analog design, the release explained.

“To overcome these challenges, the team has designed a novel framework that allows the development of analog processors that scale just like digital processors. Their chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications,” it said.

The release added that different machine learning architectures can be programmed on ARYABHAT, and like digital processors, can operate robustly across a wide range of temperatures. The researchers also say the architecture is “bias-scalable” – its performance remains the same when the operating conditions like voltage or current are modified.

The design framework was developed as part of IISc student Pratik Kumar’s PhD work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), USA, who also serves as WashU’s McDonnell Academy ambassador to IISc. The researchers have outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and are planning to work with industry partners to commercialise the technology, the release added.


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Printable version | Jul 6, 2022 10:19:49 am | https://www.thehindu.com/news/national/karnataka/iisc-researchers-develop-design-framework-for-next-generation-analog-chipsets/article65603577.ece