IIT-Madras plans centre for VLSI design, microchip making

January 04, 2011 11:16 pm | Updated October 13, 2016 04:55 pm IST - CHENNAI:

IIT-Madras plans to set up a centre of excellence for VLSI (very-large-scale integration) design and microchip making. A blue print on this will be ready in the next six months, according to Kamakoti Veezhinathan, Professor at Department of Computer Science and Engineering, IIT-Madras.

On the 24th international conference on VLSI design and the 10th international conference on Embedded Systems, Mr. Veezhinathan said at a press conference here on Tuesday that global companies such as Magma and Intel will be involved in setting up the centre.

The centre would not only create ideas in VLSI design but also pick up ideas from other departments in the institute to solve an industry problem. The centre could also seek help of the private sector.

According to Alok Mehrotra, Managing Director, Magma India, a subsidiary of the U.S.-based Magma Design Automation, the size and complexity of design being implemented in India had dramatically changed, catalysed by the success of ambitious design projects at leading semiconductor companies India centres.

Magma was also taking advantage of the key technical strengths in India. Out of the company's 667 employees, 30 people were working in India. The company's software enabled global chip companies to create integrated circuits for mobile phones, electronic games, Wi-Fi, MP3 players, digital video, networking and other electronic applications, he said.

The conference was deliberating on the trends and the road ahead as VLSI design and embedded systems are the core technologies behind all electronics used widely today in these and more domains. These three verticals are also the ones with the highest growth rates projected for India in the years ahead. The 22 regular paper sessions will contain presentations on the latest research on a range of topics, including analogue, mixed-signal, nano electronics, design tools and methodology from physical design to system-level design.

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