Cadence Design Systems, Inc, on Tuesday announced a joint development agreement with IBM to create high-performance integration-optimized ‘IP’ that will help customers deliver leading-edge designs while reducing the risk and time associated with integrating complex ‘SoC’ Designs.
Under the agreement, the companies will develop ‘DDR PHYs’, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator, a release said.
The technology will be used in servers, video games and other devices and will be available through the newly announced Cadence® Open Integration Platform.
A core component of its EDA360 vision, the Cadence Open Integration Platform comprises an integration design environment, integration—optimized IP and on—demand integration services, all facilitated by Cadence’s mixed—signal and digital design, verification and implementation technologies.
“This collaboration with Cadence combines IBM’s expertise in developing and integrating process and IP technology with Cadence’s experience in IP development to supply customers with the tools needed to build a new generation of communications infrastructure.” Marie Angelopoulos, Director, IBM Microelectronics, said.
